1 ? fn9104.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. hot plug? is a trademark of core international, inc. all other trademarks mentioned are the property of their respective owners. ISL6161 dual power distribution controller the ISL6161 is a hot swap dual supply power distribution controller that can be used in pci-express applications. two external n-channel mosfets are driven to distribute and control power while providing load fault isolation. at turn-on, the gate of each external n-channel mosfet is charged with a 10 a current source. capacitors on each gate (see the typical applic ation diagram), create a programmable ramp (soft turn-on) to control inrush currents. a built in charge pump supplies the gate drive for the 12v supply n-channel mosfet switch. over current protection is fac ilitated by two external current sense resistors and fets. when the current through either resistor exceeds the user prog rammed value the controller enters the current regulation m ode. the time-out capacitor, c tim , starts charging as the c ontroller enters the time out period. once c tim charges to a 2v threshold, both the n-channel mosfets are latched off. in the event of a hard and fast fault of at least three times the programmed current limit level, the n-channel mosfet gates are pulled low immediately before entering the time out period. the controller is reset by a rising edge on the enable pin. the ISL6161 constantly monitors both output voltages and reports either one being low on the pgood output as a low. the 12v pgood vth is ~10.8v and the 3.3v vth is ~2.8v nominally. features ? hot swap dual power distribution and control for +12v and +3.3v ? provides fault isolation ? programmable current regulation level ? programmable time out ? charge pump allows the use of n-channel mosfets ? power good and over current latch indicators ? adjustable turn-on ramp ? protection during turn-on ? two levels of current limit detection provide fast response to varying fault conditions ?1 s response time to dead short ?3 s response time to 200% current overshoot applications ? pci-express applications ? power distribution and control ? hot plug, hot swap components ordering information part number temp. range ( o c) package pkg. dwg. # ISL6161cb -0 to 70 14 ld soic m14.15 pinout ISL6161 (soic) top view typical application diagram 8 9 10 11 12 14 13 7 6 5 4 3 2 1 12vs 12vg v dd enable 3vg 3vs 12visen gnd c pump c tim r ilim pgood 3visen nc 12vs 12vg enable pgood 3vg 3vs 12visen gnd c tim r ilim c pump 3isen v dd ISL6161 12v r load r ilim c tim enable input c pump r sense 3.3v r load r sense 3.3v optional r filter c filter v dd c gate c gate data sheet november 2003
2 simplified schematic 2v v dd 12vg 12vs 12isen 3vg 3vs 3isen gnd nc c tim pgood r ilim c pump enable qpump 100 a rising enable v dd r r s qn q por clim 3x enable oc 10 a optional falling edge delay r 2r edge reset r filter c filter c pump c tim r ilim 12v to load to load oc optional latch 12vin 5vin 10 a 12v ISL6161 c gate c gate to v dd + - 12v + - r sense + - pgood + - clim 3x enable oc 10 a falling edge delay r 2r 18v + - 18v + - 12v r sense ISL6161
3 pin descriptions pin # symbol function description 1 12vs 12v source connect to source of associated ex ternal n-channel mosfet switch to sense output voltage. 2 12vg 12v gate connect to the gate of associated n-c hannel mosfet switch. a capacitor from this node to ground sets the turn-on ramp. at turn-on th is capacitor will be c harged to ~17.4v by a 10 a current source. 3v dd chip supply connect to 12v supply. this can be either connected directly to the +12v rail supplying the load voltage or to a dedicated v dd +12v supply. if the former is chosen special attention to v dd decoupling must be paid to prevent sagging as heavy loads are switched on. 4 nc not connected 5 enable enable / reset enable is used to turn-on and reset the chip. both outputs turn-on when this pin is driven low. after a current limit time out, the chip is reset by the rising edge of a reset signal applied to the enable pin. this input has 100 a pull up capability which is compatible with 3v and 5v open drain and standard logic. 6 3vg 3v gate connect to the gate of the external 3v n-channel mosfet. a capacitor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to ~11.4v by a 10 a current source. 7 3vs 3 source connect to the source side of 3v ex ternal n-channel mosfet switch to sense output voltage. 8 3visen 3v current sense connect to the load side of the 3v sense resistor to measure the voltage drop across this resistor between 3vs and 3visen pins. 9 pgood power good indicator indicates that all output voltages ar e within specification. p good is driven by an open drain n-channel mosfet. it is pulled low when any output is not within specification. 10 c tim current limit timing capacitor connect a capacitor from this pin to ground. this capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). the duration of current limit time-out (in seconds) = 200k ? x c tim (farads). 11 c pump charge pump capacitor connect a 0.1 f capacitor between this pin and v dd (pin 3). provides charge storage for 12vg drive. 12 gnd chip ground 13 r ilim current limit set resistor a resistor connected between this pin and ground determines the current level at which current limit is activated. this curre nt is determined by the ratio of the r ilim resistor to the sense resistor (r sense ). the current at current limit onset is equal to 10 a x (r ilim / r sense ). the ISL6161 is limited to a 10k ? min. value (oc vth = 100mv) resistor whereas the ISL6161 can accommodate a 5k ? resistor for a lower oc vth (50mv). 14 12visen 12v current sense connect to the load side of sense resistor to measure the voltage drop across this resistor. ISL6161
4 absolute m aximum ratings t a =25 o c thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +16v 12vg, c pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 21v 12visen, 12vs . . . . . . . . . . . . . . . . . . . . . . . . . . -5v to v dd + 0.3v 3visen, 3vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5v to 7.5v pgood, r ilim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7.5v enable , c tim , 3vg . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv (class 2) operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . +10.5v to +13.2v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 12v, c vg = 0.01 f, c tim = 0.1 f, r sense = 0.1 ? , c bulk = 220 f, esr = 0.5 ? , t a = t j = 0 o c to 70 o c, unless otherwise specified parameter symbol test conditions min typ max units 12v control section current limit threshold voltage (voltage across sense resistor) v il12v r ilim = 10k ? 92 100 108 mv r ilim = 5k ? 47 53 59 mv 3x current limit threshold voltage (voltage across sense resistor) 3xv il12v r ilim = 10k ? 250 300 350 mv r ilim = 5k ? 100 165 210 mv 20% current limit response time (current within 20% of regulated value) 20%ilrt 200% current overload, r ilim = 10k ? , r short = 6.0 ? -2- s 10% current limit response time (current within 10% of regulated value) 10%ilrt 200% current overload, r ilim = 10k ? , r short = 6.0 ? -4- s 1% current limit response time (current within 1% of regulated value) 1%ilrt 200% current overload, r ilim = 10k ? , r short = 6.0 ? -10- s response time to dead short rt short c 12vg = 0.01 f - 500 1000 ns gate turn-on time t on12v c 12vg = 0.01 f-12-ms gate turn-on current i on12v c 12vg = 0.01 f 8 10 12 a 3x gate discharge current 3xdisi 12vg = 18v 0.5 0.75 - a 12v under voltage threshold 12v vuv 10.5 10.8 11.0 v charge pumped 12vg voltage v12vg c pump = 0.1 f 16.8 17.3 17.9 v 3.3v control section current limit threshold voltage (voltage across sense resistor) v il3v r ilim = 10k ? 92 100 108 mv r ilim = 5k ? 47 53 59 mv 3x current limit threshold voltage (voltage across sense resistor) 3xv il3v r ilim = 10k ? 250 300 350 mv r ilim = 5k ? 100 155 210 mv 20% current limit response time (current within 20% of regulated value) 200% current overload, r ilim = 10k ? , r short = 2.5 ? -2- s 10% current limit response time (current within 10% of regulated value) 200% current overload, r ilim = 10k ? , r short = 2.5 ? -4- s 1% current limit response time (current within 1% of regulated value) 200% current overload, r ilim = 10k ? , r short = 2.5 ? -10- s response time to dead short rt short c vg = 0.01 f - 500 800 ns ISL6161
5 ISL6161 description and operation the ISL6161 is a multi featured +12v and +3.3v dual power supply distribution controller, features include programmable current regulation (cr) limiting and time to latch off. at turn-on, the gate capacitor of each external n-channel mosfet is charged with a 10 a current source. these capacitors create a programmable ramp (soft turn-on). a charge pump supplies the gate drive for the 12v supply control fet switch driving that gate to 17v. the load currents pass through two external current sense resistors. when the voltage ac ross either resistor quickly exceeds the user programmed current regulation voltage threshold (crvth) level, the cont roller enters current regulation. the crvth is set by the external resistor value on r ilim pin. at this time the time-out capacitor, c tim , starts charging with a 10 a current source and the controller enters the time out period. the length of the time out period is set by the single external capacitor (see table 2) placed from the c tim pin (pin 10) to ground and is characterized by a lowered gate drive voltage to the appropriate external n-channel mosfet. once c tim charges to 2v, an internal comparator is tripped resulting in both n-channel mosfets being latched off. if the voltage across the sense resistors rises sl owly in response to an oc condition, then the cr mode is entered at ~95% of the programmed cr level. this difference is due to the necessary hysteresis and response time in the cr control circuitry. table 1 shows rsense and rilim recommendations and resulting cr level for the pci-express add-in card connector sizes specified. gate turn-on time t on3v c vg = 0.01 f-5-ms gate turn-on current i on3v c vg = 0.01 f 8 10 12 a 3x gate discharge current 3xdisi c vg = 0.01 f, enable = low 0.5 0.75 - a 3.3v under voltage threshold 3.3v vuv 2.7 2.85 3.0 v 3.3vg high voltage 3vg 11.2 11.9 - v supply current and io specifications v dd supply current i vdd 4810ma v dd por rising threshold 9.5 10.0 10.7 v v dd por falling threshold 9.3 9.8 10.3 v current limit time-out t ilim c tim = 0.1 f162024ms enable pull-up voltage pwrn_v enable pin open 1.8 2.4 3.2 v enable rising threshold pwr_vth 1.1 1.5 2 v enable hysteresis pwr_hys 0.1 0.2 0.3 v enable pull-up current pwrn_i 60 80 100 a current limit time-out threshold (c tim )c tim _vth 1.8 2 2.2 v c tim charging current c tim _i 8 10 12 a c tim discharge current c tim _disi 1.7 2.6 3.5 ma c tim pull-up current c tim _disi v ctim = 8v 3.556.5ma r ilim pin current source output r ilim _io 90 100 110 a charge pump output current qpmp_io c pump = 0.1 f, c pump = 16v 320 560 800 a charge pump output voltage qpmp_vo no load 17.2 17.4 - v charge pump output voltage - loaded qpmp_vio load current = 100 a 16.2 16.7 - v charge pump por rising threshold qpmp+vth 15.6 16 16.5 v charge pump por falling threshold qpmp-vth 15.2 15.7 16.2 v electrical specifications v dd = 12v, c vg = 0.01 f, c tim = 0.1 f, r sense = 0.1 ? , c bulk = 220 f, esr = 0.5 ? , t a = t j = 0 o c to 70 o c, unless otherwise specified (continued) parameter symbol test conditions min typ max units table 1. pci-express add-in card connector r ilim (k ?) 3.3v r sense (m ?), nominal cr (a) 12v r sense (m ?), nominal cr (a) nominal crvth (mv) x1 10 30, 3.3 150, 0.7 100 4.99 15, 3.5 90, 0.6 53 ISL6161
6 the ISL6161 responds to a load short (defined as a current level 3x the oc set point with a fast transition) by immediately driving the relevant n-channel mosfet gate to 0v in ~3 s. the gate voltage is then slowly ramped up soft starting the n-channel mosfet to the programmed current regulation limit level, this is th e start of the time out period if the abnormal load condition still exists. the programmed current regulation level is held until either the oc event passes or the time out period expires. if the former is the case then the n-channel mosfet is fully enhanced and the c tim charging current is diverted away from the capacitor. if the time out period expires prior to oc resolution then both gates are quickly pulled to 0v turning off both n-channel mosfets simultaneously. upon any uv condition the pgood signal will pull low when tied high through a resistor to the logic supply. this pin is a fault indicator but not the oc latch off indicator. for an oc latch off indication, monitor ctim, pin 10. this pin will rise rapidly to 12v once the time out period expires. see block diagram for oc latch off circuit suggestion. the ISL6161 is reset by a rising edge on the enable pin and is turned on by the enable pin being driven low. ISL6161 application considerations in a non pci-express, motor drive application current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. as the ISL6161 drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. a simple method to enhance stability is provided by the substitution of a larger valu e gate resistor. typically this situation can be avoided by eliminating long point to point wiring to the load. with the enable internal pull-up the ISL6161 is well suited for implementation on either side of the connector where a motherboard prebiased conditio n or a load board staggered connection is present. in either case the ISL6161 turns on in a soft start mode protecting the supply rail from sudden current loading. during the time out delay period with the ISL6161 in current limit mode, the v gs of the external n-channel mosfets is reduced drivin g the n-channel mosfet switch into a high r ds(on) state. thus avoid extended time out periods as the external n-channel mosfets may be damaged or destroyed due to excessive internal power dissipation. refer to the mosf et manufacturers data sheet for soa information. with the high levels of inrush current e.g., highly capacitive loads and motor start up currents, choosing the current regulation (cr) level is crucial to provide both protection and still allow for this inrush current without latching off. consider this in addition to the time out delay when choosing mosfets for your design. physical layout of rsense resistors is critical to avoid inadvertently lowering the cr and trip levels. ideally trace routing between the rsense resistors and the ISL6161 is direct and as short as possible with zero current in the sense lines. open load detection can be accomplished by monitoring the isen pins. although gat ed off the external fet i dss will cause the isen pin to float above ground to some voltage when there is no attached load. if this is not desired 5k resistors from the xisen pins to ground will prevent the outputs from floating when the external switch fets are disabled and the outputs are open. for pci-express applications the ISL6161 and the isl6118 provide the fundamental hotswap function for the +12v & +3.3v main rails and th e +3.3v aux respectively as shown in figure 13. x4/x8 10 30, 3.3 40, 2.5 100 4.99 15, 3.5 20, 2.6 53 x16 10 30, 3.3 16, 6.3 100 4.99 15, 3.5 8, 6.6 53 note: nominal cr vth = rilim x 10 a. table 2. c tim capacitor nominal time out period 0.022 f4.4ms 0.047 f9.4ms 0.1 f 20ms note: nominal time-out period in seconds = c tim x 200k ?. table 1. (continued) pci-express add-in card connector r ilim (k ?) 3.3v r sense (m ?), nominal cr (a) 12v r sense (m ?), nominal cr (a) nominal crvth (mv) correct to isen and current sense resistor incorrect figure 1. sense resistor pcb layout r iset ISL6161
7 typical performance curves figure 2. supply current figure 3. r ilim source current figure 4. c tim current source figure 5. c tim oc voltage threshold figure 6. 12v uv threshold figure 7. 3.3v uv threshold 8.2 8.0 7.8 7.6 7.4 7.2 -40 -200 20406080 temperature ( o c) 8.4 supply current (ma) -30 -10 10 30 50 70 104 103 -40 -20 0 20 40 60 80 102 70 50 30 10 -10 -30 105 temperature ( o c) current ( a) -40 -20 0 20 40 60 -30 -10 10 30 50 70 80 10.7 10.6 10.5 10.4 10.3 c tim current source ( a) temperature ( o c) -40 -20 0 20 40 60 -30 -10 10 30 50 70 80 2.04 2.02 2.00 1.98 1.96 1.94 c tim oc voltage threshold (v) temperature ( o c) temperature ( o c) 12v uv threshold (v) 20 40 60 80 -40 -20 0 10.92 10.902 10.886 10.87 20 40 60 80 -40 -20 0 2.875 2.8725 2.870 2.8675 2.865 temperature ( o c) 3.3v uv threshold (v) ISL6161
8 figure 8. 12v, 3v gate drive figure 9. pump voltage figure 10. oc voltage threshold with r lim = 5k ? figure 11. oc voltage threshold with r lim = 10k ? figure 12. power on reset voltage threshold typical performance curves (continued) 12v vg 3.3vg 20 40 60 80 -40 0 -20 17.36 17.34 17.32 17.30 17.28 17.26 11.935 11.930 11.925 11.920 11.915 11.910 11.905 11.900 temperature ( o c) 3.3v gate drive (v) 12v gate drive (v) 20 40 60 80 -40 0 -20 voltage (v) temperature ( o c) 17.6 17.4 17.2 16.8 16.6 17.0 charge pump voltage no load charge pump voltage 100 a load 20 40 60 80 -40 0 -20 temperature ( o c) voltage threshold (mv) 54.5 54.0 53.5 53.0 52.5 12 oc vth 3.3 oc vth 20 40 60 80 -40 0 -20 voltage threshold (mv) 12 oc vtth 3.3 oc vth temperature ( o c) 102.5 102.0 101.5 101.0 100.5 -40 -20 0 20 40 60 80 -30 -10 10 30 50 70 10.2 10.0 9.8 9.6 power on reset (v) temperature ( o c) v dd low to high v dd high to low ISL6161
9 ISL6161 pci-express implementati on of ISL6161 and isl6118 controller intersil ISL6161 12v, 3.3v power controller intersil isl6118 dual 3.3vaux power controller 3.3v gate switch +12v gate switch +12v 3.3v gate switch +12v gate switch slot 2 pwren# slot 2 pwrgd pci-express slot 1 pci-express slot 2 slot 1 pwren# slot 1 pwrgd slot 2 pwrflt# slot 2 pwren# slot 1 pwrflt# slot 1 pwren# 3.3v +12v 3.3vaux 3.3vaux 3.3v +12v intersil ISL6161 12v, 3.3v power controller 3.3v slot 1 prsnt slot 2 prsnt 3.3vsb 3.3v 12v figure 13.
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6161 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93
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